FPGA to ASIC

        - one lonesome software engineer's trek into the darkness


Software

Apart from the commercial seats (which are 6-figure per seat per year licences), there is very little software out there for ASIC preparation and mask generation..

There's one in the GNU universe called 'Electric', and people have made chips from this, but at first glance it appears to be more based on physical layout of transistors than the interpretation of HDL and creation of gates
There's another called, promisingly enough, 'vtr' which stands for 'Verilog To Routing', which soar of implies that it's ideal for the job, however it seems to be targetted at FPGAs instead of ASICs. This leaves…
Qflow. This is a suite of open source tools that together form HDL synthesis (using Yosys), logic optimisation (using ABC), logic placement (using GreyWolf), a detail-router (using qRouter), and a layout viewer (using Magic).

So Magic it is. Well, sort of. As detailed in the blog posts, Magic works well under Linux, but I happen to use a Mac - and the compiler on the Mac is 'clang', even though it pretends to be gcc. Clang is really a C99 compiler at heart, and it likes its C to be relatively modern, with things like prototypes, and proper return definitions…

Magic was first written back in the 80's, and although it has stood the test of time very well (somewhat amazingly well, actually) it does show some of its heritage… Porting the code to a modern 64-bit clean environment, and having it compile without warnings was a major effort. Magic and its dependent tools are
big.