FPGA to ASIC

        - one lonesome software engineer's trek into the darkness


simon% qflow synthesize place route map9v3

--------------------------------
Qflow project setup
--------------------------------

No technology specified or found;  using default technology osu035

Running yosys for verilog parsing and synthesis

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2016  Clifford Wolf            |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.7+     153 (git sha1 a6ca2827, clang 8.0.0 -fPIC -Os)


-- Executing script file `map9v3.ys' --

1. Executing Liberty frontend.
Imported 39 cell types from liberty file.

2. Executing Verilog-2005 frontend.
Parsing Verilog input from `map9v3.v' to AST representation.
Generating RTLIL representation for module `\map9v3'.
Successfully finished Verilog frontend.

3. Executing SYNTH pass.

3.1. Executing HIERARCHY pass (managing design hierarchy).

3.1.1. Analyzing design hierarchy..
Top module:  \map9v3

3.1.2. Analyzing design hierarchy..
Top module:  \map9v3
Removed 0 unused modules.

3.2. Executing PROC pass (convert processes to netlists).

3.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

3.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

3.2.3. Executing PROC_INIT pass (extract init attributes).

3.2.4. Executing PROC_ARST pass (detect async resets in processes).
Found async reset \reset in `\map9v3.$proc$map9v3.v:37$1'.

3.2.5. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\map9v3.$proc$map9v3.v:37$1'.
     1/14: $0\dp[8:0] [8:1]
     2/14: $0\dp[8:0] [0]
     3/14: $0\sr[7:0] [0]
     4/14: $0\sr[7:0] [2]
     5/14: $0\sr[7:0] [3]
     6/14: $0\sr[7:0] [4]
     7/14: $0\sr[7:0] [5]
     8/14: $0\sr[7:0] [6]
     9/14: $0\sr[7:0] [7]
    10/14: $0\startbuf[0:0]
    11/14: $0\state[2:0]
    12/14: $0\counter[7:0]
    13/14: $0\done[0:0]
    14/14: $0\sr[7:0] [1]

3.2.6. Executing PROC_DLATCH pass (convert process syncs to latches).

3.2.7. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\map9v3.\dp' using process `\map9v3.$proc$map9v3.v:37$1'.
  created $adff cell `$procdff$124' with positive edge clock and positive level reset.
Creating register for signal `\map9v3.\done' using process `\map9v3.$proc$map9v3.v:37$1'.
  created $adff cell `$procdff$125' with positive edge clock and positive level reset.
Creating register for signal `\map9v3.\counter' using process `\map9v3.$proc$map9v3.v:37$1'.
  created $adff cell `$procdff$126' with positive edge clock and positive level reset.
Creating register for signal `\map9v3.\sr' using process `\map9v3.$proc$map9v3.v:37$1'.
  created $adff cell `$procdff$127' with positive edge clock and positive level reset.
Creating register for signal `\map9v3.\startbuf' using process `\map9v3.$proc$map9v3.v:37$1'.
  created $adff cell `$procdff$128' with positive edge clock and positive level reset.
Creating register for signal `\map9v3.\state' using process `\map9v3.$proc$map9v3.v:37$1'.
  created $adff cell `$procdff$129' with positive edge clock and positive level reset.

3.2.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 7 empty switches in `\map9v3.$proc$map9v3.v:37$1'.
Removing empty process `map9v3.$proc$map9v3.v:37$1'.
Cleaned up 7 empty switches.

3.3. Executing OPT_EXPR pass (perform const folding).
Replacing $eq cell `$eq$map9v3.v:39$2' (1) in module `\map9v3' with constant driver `$eq$map9v3.v:39$2_Y = \reset'.
Replacing $eq cell `$eq$map9v3.v:50$3' in module `map9v3' with $logic_not.
Replacing $eq cell `$eq$map9v3.v:66$12' in module `map9v3' with $logic_not.
Replacing $eq cell `$eq$map9v3.v:80$16' (1) in module `\map9v3' with constant driver `$eq$map9v3.v:80$16_Y = \start'.
Replacing $eq cell `$eq$map9v3.v:80$17' in module `map9v3' with inverter.

3.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \map9v3..

3.5. Executing CHECK pass (checking for obvious problems).
checking module map9v3..
found and reported 0 problems.

3.6. Executing OPT pass (performing simple optimizations).

3.6.1. Executing OPT_EXPR pass (perform const folding).

3.6.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\map9v3'.
Removed a total of 0 cells.

3.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \map9v3..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
    Root of a mux tree: $procmux$104 (pure)
    Root of a mux tree: $procmux$116 (pure)
    Root of a mux tree: $procmux$122 (pure)
    Root of a mux tree: $procmux$26 (pure)
    Root of a mux tree: $procmux$35 (pure)
    Root of a mux tree: $procmux$41 (pure)
    Root of a mux tree: $procmux$47 (pure)
    Root of a mux tree: $procmux$53 (pure)
    Root of a mux tree: $procmux$59 (pure)
    Root of a mux tree: $procmux$65 (pure)
    Root of a mux tree: $procmux$71 (pure)
    Root of a mux tree: $procmux$77 (pure)
    Root of a mux tree: $procmux$98 (pure)
  Analyzing evaluation results.
Removed 0 multiplexer ports.

3.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \map9v3.
Performed a total of 0 changes.

3.6.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\map9v3'.
Removed a total of 0 cells.

3.6.6. Executing OPT_RMDFF pass (remove dff with constant values).

3.6.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \map9v3..

3.6.8. Executing OPT_EXPR pass (perform const folding).

3.6.9. Finished OPT passes. (There is nothing left to do.)

3.7. Executing WREDUCE pass (reducing word size of cells).
Removed top 24 bits (of 32) from port A of cell map9v3.$sub$map9v3.v:51$4 ($sub).
Removed top 30 bits (of 32) from port B of cell map9v3.$add$map9v3.v:51$5 ($add).
Removed top 24 bits (of 32) from port Y of cell map9v3.$add$map9v3.v:51$5 ($add).
Removed top 24 bits (of 32) from port A of cell map9v3.$add$map9v3.v:51$5 ($add).
Removed top 2 bits (of 3) from port B of cell map9v3.$eq$map9v3.v:56$6 ($eq).
Removed top 31 bits (of 32) from port B of cell map9v3.$sub$map9v3.v:65$11 ($sub).
Removed top 24 bits (of 32) from port Y of cell map9v3.$sub$map9v3.v:65$11 ($sub).
Removed top 1 bits (of 3) from port B of cell map9v3.$eq$map9v3.v:70$13 ($eq).
Removed top 1 bits (of 3) from port B of cell map9v3.$eq$map9v3.v:75$14 ($eq).
Removed top 24 bits (of 32) from port Y of cell map9v3.$sub$map9v3.v:51$4 ($sub).
Removed top 24 bits (of 32) from wire map9v3.$add$map9v3.v:51$5_Y.
Removed top 24 bits (of 32) from wire map9v3.$sub$map9v3.v:51$4_Y.

3.8. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module map9v3:
  creating $macc model for $add$map9v3.v:51$5 ($add).
  creating $macc model for $sub$map9v3.v:51$4 ($sub).
  creating $macc model for $sub$map9v3.v:65$11 ($sub).
  merging $macc model for $sub$map9v3.v:51$4 into $add$map9v3.v:51$5.
  creating $alu model for $macc $sub$map9v3.v:65$11.
  creating $macc cell for $add$map9v3.v:51$5: $auto$alumacc.cc:354:replace_macc$132
  creating $alu cell for $sub$map9v3.v:65$11: $auto$alumacc.cc:470:replace_alu$133
  created 1 $alu and 1 $macc cells.

3.9. Executing SHARE pass (SAT-based resource sharing).

3.10. Executing OPT pass (performing simple optimizations).

3.10.1. Executing OPT_EXPR pass (perform const folding).

3.10.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\map9v3'.
Removed a total of 0 cells.

3.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \map9v3..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
    Root of a mux tree: $procmux$104 (pure)
    Root of a mux tree: $procmux$116 (pure)
    Root of a mux tree: $procmux$122 (pure)
    Root of a mux tree: $procmux$26 (pure)
    Root of a mux tree: $procmux$35 (pure)
    Root of a mux tree: $procmux$41 (pure)
    Root of a mux tree: $procmux$47 (pure)
    Root of a mux tree: $procmux$53 (pure)
    Root of a mux tree: $procmux$59 (pure)
    Root of a mux tree: $procmux$65 (pure)
    Root of a mux tree: $procmux$71 (pure)
    Root of a mux tree: $procmux$77 (pure)
    Root of a mux tree: $procmux$98 (pure)
  Analyzing evaluation results.
Removed 0 multiplexer ports.

3.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \map9v3.
Performed a total of 0 changes.

3.10.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\map9v3'.
Removed a total of 0 cells.

3.10.6. Executing OPT_RMDFF pass (remove dff with constant values).

3.10.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \map9v3..
  removing unused `$sub' cell `$sub$map9v3.v:51$4'.

3.10.8. Executing OPT_EXPR pass (perform const folding).

3.10.9. Rerunning OPT passes. (Maybe there is more to do..)

3.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \map9v3..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
    Root of a mux tree: $procmux$104 (pure)
    Root of a mux tree: $procmux$116 (pure)
    Root of a mux tree: $procmux$122 (pure)
    Root of a mux tree: $procmux$26 (pure)
    Root of a mux tree: $procmux$35 (pure)
    Root of a mux tree: $procmux$41 (pure)
    Root of a mux tree: $procmux$47 (pure)
    Root of a mux tree: $procmux$53 (pure)
    Root of a mux tree: $procmux$59 (pure)
    Root of a mux tree: $procmux$65 (pure)
    Root of a mux tree: $procmux$71 (pure)
    Root of a mux tree: $procmux$77 (pure)
    Root of a mux tree: $procmux$98 (pure)
  Analyzing evaluation results.
Removed 0 multiplexer ports.

3.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \map9v3.
Performed a total of 0 changes.

3.10.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\map9v3'.
Removed a total of 0 cells.

3.10.13. Executing OPT_RMDFF pass (remove dff with constant values).

3.10.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \map9v3..

3.10.15. Executing OPT_EXPR pass (perform const folding).

3.10.16. Finished OPT passes. (There is nothing left to do.)

3.11. Executing FSM pass (extract and optimize FSM).

3.11.1. Executing FSM_DETECT pass (finding FSMs in design).
Found FSM state register map9v3.state.

3.11.2. Executing FSM_EXTRACT pass (extracting FSM from design).
Extracting FSM `\state' from module `\map9v3'.
  found $adff cell for state register: $procdff$129
  root of input selection tree: $0\state[2:0]
  found reset state: 3'000 (from async reset)
  found ctrl input: $eq$map9v3.v:50$3_Y
  found ctrl input: $eq$map9v3.v:56$6_Y
  found ctrl input: $eq$map9v3.v:70$13_Y
  found ctrl input: $eq$map9v3.v:75$14_Y
  found ctrl input: $eq$map9v3.v:79$15_Y
  found ctrl input: $logic_and$map9v3.v:80$18_Y
  found state code: 3'100
  found state code: 3'011
  found ctrl input: $eq$map9v3.v:66$12_Y
  found state code: 3'010
  found state code: 3'001
  found ctrl output: $eq$map9v3.v:50$3_Y
  found ctrl output: $eq$map9v3.v:56$6_Y
  found ctrl output: $eq$map9v3.v:70$13_Y
  found ctrl output: $eq$map9v3.v:75$14_Y
  found ctrl output: $eq$map9v3.v:79$15_Y
  ctrl inputs: { $logic_and$map9v3.v:80$18_Y $eq$map9v3.v:66$12_Y }
  ctrl outputs: { $eq$map9v3.v:79$15_Y $eq$map9v3.v:75$14_Y $eq$map9v3.v:70$13_Y $eq$map9v3.v:56$6_Y $eq$map9v3.v:50$3_Y $0\state[2:0] }
  transition:      3'000 2'-- ->      3'001 8'00001001
  transition:      3'100 2'0- ->      3'100 8'10000100
  transition:      3'100 2'1- ->      3'000 8'10000000
  transition:      3'010 2'-- ->      3'011 8'00100011
  transition:      3'001 2'-0 ->      3'001 8'00010001
  transition:      3'001 2'-1 ->      3'010 8'00010010
  transition:      3'011 2'-- ->      3'100 8'01000100

3.11.3. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\state$136' from module `\map9v3'.

3.11.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \map9v3..
  removing unused `$logic_not' cell `$eq$map9v3.v:50$3'.
  removing unused `$eq' cell `$eq$map9v3.v:56$6'.
  removing unused `$eq' cell `$eq$map9v3.v:70$13'.
  removing unused `$eq' cell `$eq$map9v3.v:75$14'.
  removing unused `$eq' cell `$eq$map9v3.v:79$15'.
  removing unused `$mux' cell `$procmux$81'.
  removing unused `$mux' cell `$procmux$83'.
  removing unused `$mux' cell `$procmux$86'.
  removing unused `$mux' cell `$procmux$89'.
  removing unused `$mux' cell `$procmux$93'.
  removing unused `$mux' cell `$procmux$95'.
  removing unused `$mux' cell `$procmux$98'.
  removing unused `$adff' cell `$procdff$129'.

3.11.5. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\state$136' from module `\map9v3'.
  Removing unused output signal $0\state[2:0] [0].
  Removing unused output signal $0\state[2:0] [1].
  Removing unused output signal $0\state[2:0] [2].
  Removing unused output signal $eq$map9v3.v:79$15_Y.

3.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
Recoding FSM `$fsm$\state$136' from module `\map9v3' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  000 -> ----1
  100 -> ---1-
  010 -> --1--
  001 -> -1---
  011 -> 1----

3.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

FSM `$fsm$\state$136' from module `\map9v3':
-------------------------------------

  Information on FSM $fsm$\state$136 (\state):

  Number of input signals:    2
  Number of output signals:   4
  Number of state bits:       5

  Input signals:
    0: $eq$map9v3.v:66$12_Y
    1: $logic_and$map9v3.v:80$18_Y

  Output signals:
    0: $eq$map9v3.v:50$3_Y
    1: $eq$map9v3.v:56$6_Y
    2: $eq$map9v3.v:70$13_Y
    3: $eq$map9v3.v:75$14_Y

  State encoding:
    0:    5'----1  
    1:    5'---1-
    2:    5'--1--
    3:    5'-1---
    4:    5'1----

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 2'--   ->     3 4'0001
      1:     1 2'1-   ->     0 4'0000
      2:     1 2'0-   ->     1 4'0000
      3:     2 2'--   ->     4 4'0100
      4:     3 2'-1   ->     2 4'0010
      5:     3 2'-0   ->     3 4'0010
      6:     4 2'--   ->     1 4'1000

-------------------------------------

3.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
Mapping FSM `$fsm$\state$136' from module `\map9v3'.

3.12. Executing OPT pass (performing simple optimizations).

3.12.1. Executing OPT_EXPR pass (perform const folding).
Replacing $eq cell `$auto$fsm_map.cc:77:implement_pattern_cache$161' in module `map9v3' with inverter.
Replacing $eq cell `$auto$fsm_map.cc:77:implement_pattern_cache$148' (1) in module `\map9v3' with constant driver `$auto$fsm_map.cc:74:implement_pattern_cache$147 = $logic_and$map9v3.v:80$18_Y'.
Replacing $eq cell `$auto$fsm_map.cc:77:implement_pattern_cache$152' in module `map9v3' with inverter.
Replacing $eq cell `$auto$fsm_map.cc:77:implement_pattern_cache$157' (1) in module `\map9v3' with constant driver `$auto$fsm_map.cc:74:implement_pattern_cache$156 = $eq$map9v3.v:66$12_Y'.

3.12.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\map9v3'.
Removed a total of 0 cells.

3.12.3. Executing OPT_RMDFF pass (remove dff with constant values).

3.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \map9v3..

3.12.5. Finished fast OPT passes.

3.13. Executing MEMORY pass.

3.13.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).

3.13.2. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \map9v3..

3.13.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

3.13.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \map9v3..

3.13.5. Executing MEMORY_COLLECT pass (generating $mem cells).

3.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \map9v3..

3.15. Executing OPT pass (performing simple optimizations).

3.15.1. Executing OPT_EXPR pass (perform const folding).
Replacing $mux cell `$procmux$107' in module `map9v3' with or-gate.

3.15.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\map9v3'.
Removed a total of 0 cells.

3.15.3. Executing OPT_RMDFF pass (remove dff with constant values).

3.15.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \map9v3..

3.15.5. Finished fast OPT passes.

3.16. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).

3.17. Executing OPT pass (performing simple optimizations).

3.17.1. Executing OPT_EXPR pass (perform const folding).

3.17.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\map9v3'.
Removed a total of 0 cells.

3.17.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \map9v3..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
    Root of a mux tree: $procmux$104 (pure)
    Root of a mux tree: $procmux$116 (pure)
    Root of a mux tree: $procmux$122 (pure)
    Root of a mux tree: $procmux$26 (pure)
    Root of a mux tree: $procmux$35 (pure)
    Root of a mux tree: $procmux$41 (pure)
    Root of a mux tree: $procmux$47 (pure)
    Root of a mux tree: $procmux$53 (pure)
    Root of a mux tree: $procmux$59 (pure)
    Root of a mux tree: $procmux$65 (pure)
    Root of a mux tree: $procmux$71 (pure)
    Root of a mux tree: $procmux$77 (pure)
  Analyzing evaluation results.
Removed 0 multiplexer ports.

3.17.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \map9v3.
    New input vector for $reduce_or cell $auto$fsm_map.cc:144:implement_pattern_cache$164: { \state [0] $auto$fsm_map.cc:118:implement_pattern_cache$162 }
    New input vector for $reduce_or cell $auto$fsm_map.cc:144:implement_pattern_cache$155: { \state [4] $auto$fsm_map.cc:118:implement_pattern_cache$153 }
  Optimizing cells in module \map9v3.
Performed a total of 2 changes.

3.17.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\map9v3'.
Removed a total of 0 cells.

3.17.6. Executing OPT_RMDFF pass (remove dff with constant values).

3.17.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \map9v3..

3.17.8. Executing OPT_EXPR pass (perform const folding).

3.17.9. Rerunning OPT passes. (Maybe there is more to do..)

3.17.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \map9v3..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
    Root of a mux tree: $procmux$104 (pure)
    Root of a mux tree: $procmux$116 (pure)
    Root of a mux tree: $procmux$122 (pure)
    Root of a mux tree: $procmux$26 (pure)
    Root of a mux tree: $procmux$35 (pure)
    Root of a mux tree: $procmux$41 (pure)
    Root of a mux tree: $procmux$47 (pure)
    Root of a mux tree: $procmux$53 (pure)
    Root of a mux tree: $procmux$59 (pure)
    Root of a mux tree: $procmux$65 (pure)
    Root of a mux tree: $procmux$71 (pure)
    Root of a mux tree: $procmux$77 (pure)
  Analyzing evaluation results.
Removed 0 multiplexer ports.

3.17.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \map9v3.
Performed a total of 0 changes.

3.17.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\map9v3'.
Removed a total of 0 cells.

3.17.13. Executing OPT_RMDFF pass (remove dff with constant values).

3.17.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \map9v3..

3.17.15. Executing OPT_EXPR pass (perform const folding).

3.17.16. Finished OPT passes. (There is nothing left to do.)

3.18. Executing TECHMAP pass (map to technology primitives).

3.18.1. Executing Verilog-2005 frontend.
Parsing Verilog input from `' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.
Mapping map9v3.$xor$map9v3.v:64$7 ($xor) with simplemap.
Mapping map9v3.$xor$map9v3.v:64$8 ($xor) with simplemap.
Mapping map9v3.$xor$map9v3.v:64$9 ($xor) with simplemap.
Mapping map9v3.$not$map9v3.v:64$10 ($not) with simplemap.
Mapping map9v3.$eq$map9v3.v:66$12 ($logic_not) with simplemap.
Mapping map9v3.$auto$fsm_map.cc:144:implement_pattern_cache$164 ($reduce_or) with simplemap.
Mapping map9v3.$eq$map9v3.v:80$17 ($not) with simplemap.
Mapping map9v3.$logic_and$map9v3.v:80$18 ($logic_and) with simplemap.
Mapping map9v3.$procmux$20 ($mux) with simplemap.
Mapping map9v3.$procmux$23 ($mux) with simplemap.
Mapping map9v3.$procmux$26 ($mux) with simplemap.
Mapping map9v3.$procmux$29 ($mux) with simplemap.
Mapping map9v3.$procmux$32 ($mux) with simplemap.
Mapping map9v3.$procmux$35 ($mux) with simplemap.
Mapping map9v3.$procmux$38 ($mux) with simplemap.
Mapping map9v3.$procmux$41 ($mux) with simplemap.
Mapping map9v3.$procmux$44 ($mux) with simplemap.
Mapping map9v3.$procmux$47 ($mux) with simplemap.
Mapping map9v3.$procmux$50 ($mux) with simplemap.
Mapping map9v3.$procmux$53 ($mux) with simplemap.
Mapping map9v3.$procmux$56 ($mux) with simplemap.
Mapping map9v3.$procmux$59 ($mux) with simplemap.
Mapping map9v3.$procmux$62 ($mux) with simplemap.
Mapping map9v3.$procmux$65 ($mux) with simplemap.
Mapping map9v3.$procmux$68 ($mux) with simplemap.
Mapping map9v3.$procmux$71 ($mux) with simplemap.
Mapping map9v3.$procmux$74 ($mux) with simplemap.
Mapping map9v3.$auto$fsm_map.cc:172:map_fsm$144 ($adff) with simplemap.
Mapping map9v3.$procmux$77 ($mux) with simplemap.
Mapping map9v3.$auto$fsm_map.cc:121:implement_pattern_cache$150 ($and) with simplemap.
Mapping map9v3.$auto$fsm_map.cc:121:implement_pattern_cache$163 ($and) with simplemap.
Mapping map9v3.$auto$fsm_map.cc:77:implement_pattern_cache$152 ($not) with simplemap.
Mapping map9v3.$auto$fsm_map.cc:77:implement_pattern_cache$161 ($not) with simplemap.
Mapping map9v3.$auto$fsm_map.cc:121:implement_pattern_cache$154 ($and) with simplemap.
Mapping map9v3.$auto$fsm_map.cc:121:implement_pattern_cache$159 ($and) with simplemap.
Mapping map9v3.$auto$fsm_map.cc:144:implement_pattern_cache$155 ($reduce_or) with simplemap.
Mapping map9v3.$procmux$101 ($mux) with simplemap.
Mapping map9v3.$procmux$104 ($mux) with simplemap.
Mapping map9v3.$procmux$107 ($or) with simplemap.
Mapping map9v3.$procmux$110 ($mux) with simplemap.
Mapping map9v3.$procmux$113 ($mux) with simplemap.

3.18.2. Executing AST frontend in derive mode using pre-parsed AST for module `\_90_alu'.
Parameter \A_SIGNED = 0
Parameter \B_SIGNED = 0
Parameter \A_WIDTH = 8
Parameter \B_WIDTH = 1
Parameter \Y_WIDTH = 8
Generating RTLIL representation for module `$paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=8\B_WIDTH=1\Y_WIDTH=8'.

3.18.3. Continuing TECHMAP pass.
Mapping map9v3.$auto$alumacc.cc:470:replace_alu$133 using $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=8\B_WIDTH=1\Y_WIDTH=8.
Mapping map9v3.$procmux$116 ($mux) with simplemap.
Mapping map9v3.$auto$alumacc.cc:354:replace_macc$132 ($macc) with maccmap.
  sub \N [8:1] (8 bits, unsigned)
  add 8'00000010 (8 bits, unsigned)
Mapping map9v3.$procmux$119 ($mux) with simplemap.
Mapping map9v3.$procmux$122 ($mux) with simplemap.
Mapping map9v3.$procdff$124 ($adff) with simplemap.
Mapping map9v3.$procdff$125 ($adff) with simplemap.
Mapping map9v3.$procdff$126 ($adff) with simplemap.
Mapping map9v3.$procdff$127 ($adff) with simplemap.
Mapping map9v3.$procdff$128 ($adff) with simplemap.
Mapping map9v3.$auto$maccmap.cc:55:add$307 ($not) with simplemap.

3.18.4. Executing AST frontend in derive mode using pre-parsed AST for module `\_90_alu'.
Parameter \A_SIGNED = 0
Parameter \B_SIGNED = 0
Parameter \A_WIDTH = 8
Parameter \B_WIDTH = 8
Parameter \Y_WIDTH = 8
Generating RTLIL representation for module `$paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=8\B_WIDTH=8\Y_WIDTH=8'.

3.18.5. Continuing TECHMAP pass.
Mapping map9v3.$auto$maccmap.cc:240:synth$309 using $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=8\B_WIDTH=8\Y_WIDTH=8.
Mapping map9v3.$techmap$auto$alumacc.cc:470:replace_alu$133.$xor$:262$304 ($xor) with simplemap.
Mapping map9v3.$techmap$auto$alumacc.cc:470:replace_alu$133.$xor$:263$305 ($xor) with simplemap.
Mapping map9v3.$techmap$auto$alumacc.cc:470:replace_alu$133.$and$:260$303 ($and) with simplemap.

3.18.6. Executing AST frontend in derive mode using pre-parsed AST for module `\_90_lcu'.
Parameter \WIDTH = 8
Generating RTLIL representation for module `$paramod\_90_lcu\WIDTH=8'.

3.18.7. Executing PROC pass (convert processes to netlists).

3.18.7.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

3.18.7.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

3.18.7.3. Executing PROC_INIT pass (extract init attributes).

3.18.7.4. Executing PROC_ARST pass (detect async resets in processes).

3.18.7.5. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod\_90_lcu\WIDTH=8.$proc$:207$397'.
     1/16: $0\p[7:0] [6]
     2/16: $0\g[7:0] [6]
     3/16: $0\p[7:0] [4]
     4/16: $0\g[7:0] [4]
     5/16: $0\p[7:0] [2]
     6/16: $0\g[7:0] [2]
     7/16: $0\p[7:0] [5]
     8/16: $0\g[7:0] [5]
     9/16: $0\p[7:0] [7]
    10/16: $0\g[7:0] [7]
    11/16: $0\p[7:0] [3]
    12/16: $0\g[7:0] [3]
    13/16: $0\p[7:0] [1]
    14/16: $0\g[7:0] [1]
    15/16: $0\g[7:0] [0]
    16/16: $0\p[7:0] [0]

3.18.7.6. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod\_90_lcu\WIDTH=8.\g' from process `$paramod\_90_lcu\WIDTH=8.$proc$:207$397'.
No latch inferred for signal `$paramod\_90_lcu\WIDTH=8.\p' from process `$paramod\_90_lcu\WIDTH=8.$proc$:207$397'.

3.18.7.7. Executing PROC_DFF pass (convert process syncs to FFs).

3.18.7.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod\_90_lcu\WIDTH=8.$proc$:207$397'.
Cleaned up 0 empty switches.

3.18.8. Executing OPT pass (performing simple optimizations).

3.18.8.1. Executing OPT_EXPR pass (perform const folding).

3.18.8.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod\_90_lcu\WIDTH=8'.
Removed a total of 0 cells.

3.18.8.3. Executing OPT_RMDFF pass (remove dff with constant values).

3.18.8.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module $paramod\_90_lcu\WIDTH=8..
  removing unused `$and' cell `$and$:222$402'.
  removing unused `$and' cell `$and$:222$414'.
  removing unused `$and' cell `$and$:222$420'.
  removing unused `$and' cell `$and$:230$423'.
  removing unused `$and' cell `$and$:230$426'.
  removing unused `$and' cell `$and$:230$429'.
  removing unused `$and' cell `$and$:230$432'.
  removing unused non-port wire \j.
  removing unused non-port wire \i.
  removed 2 unused temporary wires.

3.18.8.5. Finished fast OPT passes.

3.18.9. Continuing TECHMAP pass.
Mapping map9v3.$auto$alumacc.cc:470:replace_alu$133.lcu using $paramod\_90_lcu\WIDTH=8.
Mapping map9v3.$techmap$auto$alumacc.cc:470:replace_alu$133.$ternary$:258$302 ($mux) with simplemap.
Mapping map9v3.$techmap$auto$alumacc.cc:470:replace_alu$133.$not$:258$301 ($not) with simplemap.
Mapping map9v3.$auto$alumacc.cc:470:replace_alu$133.B_conv ($pos) with simplemap.
Mapping map9v3.$auto$alumacc.cc:470:replace_alu$133.A_conv ($pos) with simplemap.
Mapping map9v3.$techmap$auto$alumacc.cc:470:replace_alu$133.lcu.$and$:212$398 ($and) with simplemap.
Mapping map9v3.$techmap$auto$alumacc.cc:470:replace_alu$133.lcu.$and$:221$400 ($and) with simplemap.
Mapping map9v3.$techmap$auto$alumacc.cc:470:replace_alu$133.lcu.$and$:221$403 ($and) with simplemap.
Mapping map9v3.$techmap$auto$alumacc.cc:470:replace_alu$133.lcu.$and$:221$406 ($and) with simplemap.
Mapping map9v3.$techmap$auto$alumacc.cc:470:replace_alu$133.lcu.$and$:221$409 ($and) with simplemap.
Mapping map9v3.$techmap$auto$alumacc.cc:470:replace_alu$133.lcu.$and$:221$412 ($and) with simplemap.
Mapping map9v3.$techmap$auto$alumacc.cc:470:replace_alu$133.lcu.$and$:221$415 ($and) with simplemap.
Mapping map9v3.$techmap$auto$alumacc.cc:470:replace_alu$133.lcu.$and$:221$418 ($and) with simplemap.
Mapping map9v3.$techmap$auto$alumacc.cc:470:replace_alu$133.lcu.$and$:222$405 ($and) with simplemap.
Mapping map9v3.$techmap$auto$alumacc.cc:470:replace_alu$133.lcu.$and$:222$408 ($and) with simplemap.
Mapping map9v3.$techmap$auto$alumacc.cc:470:replace_alu$133.lcu.$and$:222$411 ($and) with simplemap.
Mapping map9v3.$techmap$auto$alumacc.cc:470:replace_alu$133.lcu.$and$:222$417 ($and) with simplemap.
Mapping map9v3.$techmap$auto$alumacc.cc:470:replace_alu$133.lcu.$and$:229$421 ($and) with simplemap.
Mapping map9v3.$techmap$auto$alumacc.cc:470:replace_alu$133.lcu.$and$:229$424 ($and) with simplemap.
Mapping map9v3.$techmap$auto$alumacc.cc:470:replace_alu$133.lcu.$and$:229$427 ($and) with simplemap.
Mapping map9v3.$techmap$auto$alumacc.cc:470:replace_alu$133.lcu.$and$:229$430 ($and) with simplemap.
Mapping map9v3.$techmap$auto$alumacc.cc:470:replace_alu$133.lcu.$or$:212$399 ($or) with simplemap.
Mapping map9v3.$techmap$auto$alumacc.cc:470:replace_alu$133.lcu.$or$:221$401 ($or) with simplemap.
Mapping map9v3.$techmap$auto$alumacc.cc:470:replace_alu$133.lcu.$or$:221$404 ($or) with simplemap.
Mapping map9v3.$techmap$auto$alumacc.cc:470:replace_alu$133.lcu.$or$:221$407 ($or) with simplemap.
Mapping map9v3.$techmap$auto$alumacc.cc:470:replace_alu$133.lcu.$or$:221$410 ($or) with simplemap.
Mapping map9v3.$techmap$auto$alumacc.cc:470:replace_alu$133.lcu.$or$:221$413 ($or) with simplemap.
Mapping map9v3.$techmap$auto$alumacc.cc:470:replace_alu$133.lcu.$or$:221$416 ($or) with simplemap.
Mapping map9v3.$techmap$auto$alumacc.cc:470:replace_alu$133.lcu.$or$:221$419 ($or) with simplemap.
Mapping map9v3.$techmap$auto$alumacc.cc:470:replace_alu$133.lcu.$or$:229$422 ($or) with simplemap.
Mapping map9v3.$techmap$auto$alumacc.cc:470:replace_alu$133.lcu.$or$:229$425 ($or) with simplemap.
Mapping map9v3.$techmap$auto$alumacc.cc:470:replace_alu$133.lcu.$or$:229$428 ($or) with simplemap.
Mapping map9v3.$techmap$auto$alumacc.cc:470:replace_alu$133.lcu.$or$:229$431 ($or) with simplemap.
Mapping map9v3.$techmap$auto$maccmap.cc:240:synth$309.$xor$:262$353 ($xor) with simplemap.
Mapping map9v3.$techmap$auto$maccmap.cc:240:synth$309.$xor$:263$354 ($xor) with simplemap.
Mapping map9v3.$techmap$auto$maccmap.cc:240:synth$309.$and$:260$352 ($and) with simplemap.
Mapping map9v3.$auto$maccmap.cc:240:synth$309.lcu using $paramod\_90_lcu\WIDTH=8.
Mapping map9v3.$techmap$auto$maccmap.cc:240:synth$309.$ternary$:258$351 ($mux) with simplemap.
Mapping map9v3.$techmap$auto$maccmap.cc:240:synth$309.$not$:258$350 ($not) with simplemap.
Mapping map9v3.$auto$maccmap.cc:240:synth$309.B_conv ($pos) with simplemap.
Mapping map9v3.$auto$maccmap.cc:240:synth$309.A_conv ($pos) with simplemap.
Mapping map9v3.$techmap$auto$maccmap.cc:240:synth$309.lcu.$and$:212$398 ($and) with simplemap.
Mapping map9v3.$techmap$auto$maccmap.cc:240:synth$309.lcu.$and$:221$400 ($and) with simplemap.
Mapping map9v3.$techmap$auto$maccmap.cc:240:synth$309.lcu.$and$:221$403 ($and) with simplemap.
Mapping map9v3.$techmap$auto$maccmap.cc:240:synth$309.lcu.$and$:221$406 ($and) with simplemap.
Mapping map9v3.$techmap$auto$maccmap.cc:240:synth$309.lcu.$and$:221$409 ($and) with simplemap.
Mapping map9v3.$techmap$auto$maccmap.cc:240:synth$309.lcu.$and$:221$412 ($and) with simplemap.
Mapping map9v3.$techmap$auto$maccmap.cc:240:synth$309.lcu.$and$:221$415 ($and) with simplemap.
Mapping map9v3.$techmap$auto$maccmap.cc:240:synth$309.lcu.$and$:221$418 ($and) with simplemap.
Mapping map9v3.$techmap$auto$maccmap.cc:240:synth$309.lcu.$and$:222$405 ($and) with simplemap.
Mapping map9v3.$techmap$auto$maccmap.cc:240:synth$309.lcu.$and$:222$408 ($and) with simplemap.
Mapping map9v3.$techmap$auto$maccmap.cc:240:synth$309.lcu.$and$:222$411 ($and) with simplemap.
Mapping map9v3.$techmap$auto$maccmap.cc:240:synth$309.lcu.$and$:222$417 ($and) with simplemap.
Mapping map9v3.$techmap$auto$maccmap.cc:240:synth$309.lcu.$and$:229$421 ($and) with simplemap.
Mapping map9v3.$techmap$auto$maccmap.cc:240:synth$309.lcu.$and$:229$424 ($and) with simplemap.
Mapping map9v3.$techmap$auto$maccmap.cc:240:synth$309.lcu.$and$:229$427 ($and) with simplemap.
Mapping map9v3.$techmap$auto$maccmap.cc:240:synth$309.lcu.$and$:229$430 ($and) with simplemap.
Mapping map9v3.$techmap$auto$maccmap.cc:240:synth$309.lcu.$or$:212$399 ($or) with simplemap.
Mapping map9v3.$techmap$auto$maccmap.cc:240:synth$309.lcu.$or$:221$401 ($or) with simplemap.
Mapping map9v3.$techmap$auto$maccmap.cc:240:synth$309.lcu.$or$:221$404 ($or) with simplemap.
Mapping map9v3.$techmap$auto$maccmap.cc:240:synth$309.lcu.$or$:221$407 ($or) with simplemap.
Mapping map9v3.$techmap$auto$maccmap.cc:240:synth$309.lcu.$or$:221$410 ($or) with simplemap.
Mapping map9v3.$techmap$auto$maccmap.cc:240:synth$309.lcu.$or$:221$413 ($or) with simplemap.
Mapping map9v3.$techmap$auto$maccmap.cc:240:synth$309.lcu.$or$:221$416 ($or) with simplemap.
Mapping map9v3.$techmap$auto$maccmap.cc:240:synth$309.lcu.$or$:221$419 ($or) with simplemap.
Mapping map9v3.$techmap$auto$maccmap.cc:240:synth$309.lcu.$or$:229$422 ($or) with simplemap.
Mapping map9v3.$techmap$auto$maccmap.cc:240:synth$309.lcu.$or$:229$425 ($or) with simplemap.
Mapping map9v3.$techmap$auto$maccmap.cc:240:synth$309.lcu.$or$:229$428 ($or) with simplemap.
Mapping map9v3.$techmap$auto$maccmap.cc:240:synth$309.lcu.$or$:229$431 ($or) with simplemap.
No more expansions possible.

3.19. Executing OPT pass (performing simple optimizations).

3.19.1. Executing OPT_EXPR pass (perform const folding).
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$443' (0) in module `\map9v3' with constant driver `$techmap$auto$alumacc.cc:470:replace_alu$133.$not$:258$301_Y [2] = 1'1'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$435' (011) in module `\map9v3' with constant driver `$techmap$auto$alumacc.cc:470:replace_alu$133.$ternary$:258$302_Y [2] = 1'1'.
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$444' (0) in module `\map9v3' with constant driver `$techmap$auto$alumacc.cc:470:replace_alu$133.$not$:258$301_Y [3] = 1'1'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$436' (011) in module `\map9v3' with constant driver `$techmap$auto$alumacc.cc:470:replace_alu$133.$ternary$:258$302_Y [3] = 1'1'.
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$445' (0) in module `\map9v3' with constant driver `$techmap$auto$alumacc.cc:470:replace_alu$133.$not$:258$301_Y [4] = 1'1'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$437' (011) in module `\map9v3' with constant driver `$techmap$auto$alumacc.cc:470:replace_alu$133.$ternary$:258$302_Y [4] = 1'1'.
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$446' (0) in module `\map9v3' with constant driver `$techmap$auto$alumacc.cc:470:replace_alu$133.$not$:258$301_Y [5] = 1'1'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$438' (011) in module `\map9v3' with constant driver `$techmap$auto$alumacc.cc:470:replace_alu$133.$ternary$:258$302_Y [5] = 1'1'.
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$447' (0) in module `\map9v3' with constant driver `$techmap$auto$alumacc.cc:470:replace_alu$133.$not$:258$301_Y [6] = 1'1'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$439' (011) in module `\map9v3' with constant driver `$techmap$auto$alumacc.cc:470:replace_alu$133.$ternary$:258$302_Y [6] = 1'1'.
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$448' (0) in module `\map9v3' with constant driver `$techmap$auto$alumacc.cc:470:replace_alu$133.$not$:258$301_Y [7] = 1'1'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$440' (011) in module `\map9v3' with constant driver `$techmap$auto$alumacc.cc:470:replace_alu$133.$ternary$:258$302_Y [7] = 1'1'.
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$441' (1) in module `\map9v3' with constant driver `$techmap$auto$alumacc.cc:470:replace_alu$133.$not$:258$301_Y [0] = 1'0'.
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$442' (0) in module `\map9v3' with constant driver `$techmap$auto$alumacc.cc:470:replace_alu$133.$not$:258$301_Y [1] = 1'1'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$433' (101) in module `\map9v3' with constant driver `$techmap$auto$alumacc.cc:470:replace_alu$133.$ternary$:258$302_Y [0] = 1'0'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$355' (?0) in module `\map9v3' with constant driver `$techmap$auto$alumacc.cc:470:replace_alu$133.$xor$:262$304_Y [0] = \counter [0]'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$449' (and_or_buffer) in module `\map9v3' with constant driver `$techmap$auto$alumacc.cc:470:replace_alu$133.lcu.$and$:212$398_Y = \counter [0]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$434' (011) in module `\map9v3' with constant driver `$techmap$auto$alumacc.cc:470:replace_alu$133.$ternary$:258$302_Y [1] = 1'1'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$372' (const_and) in module `\map9v3' with constant driver `$techmap$auto$alumacc.cc:470:replace_alu$133.$and$:260$303_Y [0] = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$465' (and_or_buffer) in module `\map9v3' with constant driver `$auto$alumacc.cc:484:replace_alu$135 [0] = \counter [0]'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$374' (and_or_buffer) in module `\map9v3' with constant driver `$techmap$auto$alumacc.cc:470:replace_alu$133.$and$:260$303_Y [2] = \counter [2]'.
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$277' (double_invert) in module `\map9v3' with constant driver `$auto$fsm_map.cc:74:implement_pattern_cache$160 = $auto$simplemap.cc:168:logic_reduce$221'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$373' (and_or_buffer) in module `\map9v3' with constant driver `$techmap$auto$alumacc.cc:470:replace_alu$133.$and$:260$303_Y [1] = \counter [1]'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$375' (and_or_buffer) in module `\map9v3' with constant driver `$techmap$auto$alumacc.cc:470:replace_alu$133.$and$:260$303_Y [3] = \counter [3]'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$376' (and_or_buffer) in module `\map9v3' with constant driver `$techmap$auto$alumacc.cc:470:replace_alu$133.$and$:260$303_Y [4] = \counter [4]'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$377' (and_or_buffer) in module `\map9v3' with constant driver `$techmap$auto$alumacc.cc:470:replace_alu$133.$and$:260$303_Y [5] = \counter [5]'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$378' (and_or_buffer) in module `\map9v3' with constant driver `$techmap$auto$alumacc.cc:470:replace_alu$133.$and$:260$303_Y [6] = \counter [6]'.
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$510' (double_invert) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.$not$:258$350_Y [0] = \N [1]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$502' (??0) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.$ternary$:258$351_Y [0] = $auto$rtlil.cc:1602:Not$308 [0]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$485' (?0) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.$xor$:263$354_Y [0] = $techmap$auto$maccmap.cc:240:synth$309.$xor$:262$353_Y [0]'.
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$511' (double_invert) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.$not$:258$350_Y [1] = \N [2]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$503' (??0) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.$ternary$:258$351_Y [1] = $auto$rtlil.cc:1602:Not$308 [1]'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$494' (and_or_buffer) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.$and$:260$352_Y [0] = $auto$rtlil.cc:1602:Not$308 [0]'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$518' (const_and) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.lcu.$and$:212$398_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$534' (and_or_buffer) in module `\map9v3' with constant driver `$auto$maccmap.cc:247:synth$312 [0] = $auto$rtlil.cc:1602:Not$308 [0]'.
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$512' (0) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.$not$:258$350_Y [2] = 1'1'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$504' (010) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.$ternary$:258$351_Y [2] = 1'0'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$479' (?0) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.$xor$:262$353_Y [2] = $auto$rtlil.cc:1602:Not$308 [2]'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$495' (and_or_buffer) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.$and$:260$352_Y [1] = $auto$rtlil.cc:1602:Not$308 [1]'.
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$513' (0) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.$not$:258$350_Y [3] = 1'1'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$505' (010) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.$ternary$:258$351_Y [3] = 1'0'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$480' (?0) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.$xor$:262$353_Y [3] = $auto$rtlil.cc:1602:Not$308 [3]'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$496' (const_and) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.$and$:260$352_Y [2] = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$543' (and_or_buffer) in module `\map9v3' with constant driver `$auto$maccmap.cc:247:synth$312 [2] = $techmap$auto$maccmap.cc:240:synth$309.lcu.$and$:229$424_Y'.
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$514' (0) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.$not$:258$350_Y [4] = 1'1'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$506' (010) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.$ternary$:258$351_Y [4] = 1'0'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$481' (?0) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.$xor$:262$353_Y [4] = $auto$rtlil.cc:1602:Not$308 [4]'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$497' (const_and) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.$and$:260$352_Y [3] = 1'0'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$520' (const_and) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.lcu.$and$:221$403_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$536' (00) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.lcu.$or$:221$404_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$539' (and_or_buffer) in module `\map9v3' with constant driver `$auto$maccmap.cc:247:synth$312 [3] = $techmap$auto$maccmap.cc:240:synth$309.lcu.$and$:221$412_Y'.
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$515' (0) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.$not$:258$350_Y [5] = 1'1'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$507' (010) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.$ternary$:258$351_Y [5] = 1'0'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$482' (?0) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.$xor$:262$353_Y [5] = $auto$rtlil.cc:1602:Not$308 [5]'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$498' (const_and) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.$and$:260$352_Y [4] = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$544' (and_or_buffer) in module `\map9v3' with constant driver `$auto$maccmap.cc:247:synth$312 [4] = $techmap$auto$maccmap.cc:240:synth$309.lcu.$and$:229$427_Y'.
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$516' (0) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.$not$:258$350_Y [6] = 1'1'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$508' (010) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.$ternary$:258$351_Y [6] = 1'0'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$483' (?0) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.$xor$:262$353_Y [6] = $auto$rtlil.cc:1602:Not$308 [6]'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$499' (const_and) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.$and$:260$352_Y [5] = 1'0'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$521' (const_and) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.lcu.$and$:221$406_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$537' (00) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.lcu.$or$:221$407_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$542' (and_or_buffer) in module `\map9v3' with constant driver `$auto$maccmap.cc:247:synth$312 [5] = $techmap$auto$maccmap.cc:240:synth$309.lcu.$and$:229$421_Y'.
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$517' (0) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.$not$:258$350_Y [7] = 1'1'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$509' (010) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.$ternary$:258$351_Y [7] = 1'0'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$484' (?0) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.$xor$:262$353_Y [7] = $auto$rtlil.cc:1602:Not$308 [7]'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$500' (const_and) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.$and$:260$352_Y [6] = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$545' (and_or_buffer) in module `\map9v3' with constant driver `$auto$maccmap.cc:247:synth$312 [6] = $techmap$auto$maccmap.cc:240:synth$309.lcu.$and$:229$430_Y'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$379' (and_or_buffer) in module `\map9v3' with constant driver `$techmap$auto$alumacc.cc:470:replace_alu$133.$and$:260$303_Y [7] = \counter [7]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$371' (0?) in module `\map9v3' with constant driver `$techmap$auto$alumacc.cc:470:replace_alu$133.$xor$:263$305_Y [8] = $auto$alumacc.cc:484:replace_alu$135 [7]'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$524' (const_and) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.lcu.$and$:221$415_Y = 1'0'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$501' (const_and) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.$and$:260$352_Y [7] = 1'0'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$522' (const_and) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.lcu.$and$:221$409_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$538' (00) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.lcu.$or$:221$410_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$540' (00) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.lcu.$or$:221$416_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$541' (and_or_buffer) in module `\map9v3' with constant driver `$auto$maccmap.cc:247:synth$312 [7] = $techmap$auto$maccmap.cc:240:synth$309.lcu.$and$:221$418_Y'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$493' (0?) in module `\map9v3' with constant driver `$techmap$auto$maccmap.cc:240:synth$309.$xor$:263$354_Y [8] = $techmap$auto$maccmap.cc:240:synth$309.lcu.$and$:221$418_Y'.

3.19.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\map9v3'.
Removed a total of 0 cells.

3.19.3. Executing OPT_RMDFF pass (remove dff with constant values).

3.19.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \map9v3..
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$453'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$455'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$456'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$459'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$460'.
  removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$469'.
  removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$471'.
  removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$472'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$525'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$528'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$529'.

3.19.5. Finished fast OPT passes.

3.20. Executing ABC pass (technology mapping using ABC).

3.20.1. Extracting gate netlist of module `\map9v3' to `/input.blif'..
Extracted 143 gates and 187 wires to a netlist network with 42 inputs and 30 outputs.

3.20.1.1. Executing ABC.
Running ABC command: /yosys-abc -s -f /abc.script 2>&1
ABC: ABC command line: "source /abc.script".
ABC: 
ABC: + read_blif /input.blif 
ABC: + read_library /stdcells.genlib 
ABC: Entered genlib library with 15 gates from file "/stdcells.genlib".
ABC: + strash 
ABC: + dretime 
ABC: + map 
ABC: + write_blif /output.blif 

3.20.1.2. Re-integrating ABC results.
ABC RESULTS:               AND cells:       18
ABC RESULTS:              AOI3 cells:        1
ABC RESULTS:               MUX cells:       51
ABC RESULTS:              NAND cells:        4
ABC RESULTS:               NOR cells:        8
ABC RESULTS:               NOT cells:       11
ABC RESULTS:              OAI3 cells:        4
ABC RESULTS:                OR cells:        3
ABC RESULTS:              XNOR cells:        4
ABC RESULTS:               XOR cells:       14
ABC RESULTS:        internal signals:      115
ABC RESULTS:           input signals:       42
ABC RESULTS:          output signals:       30
Removing temp directory.

3.21. Executing OPT pass (performing simple optimizations).

3.21.1. Executing OPT_EXPR pass (perform const folding).
Optimizing away select inverter for $_MUX_ cell `$abc$546$auto$blifparse.cc:346:parse_blif$653' in module `map9v3'.
Optimizing away select inverter for $_MUX_ cell `$abc$546$auto$blifparse.cc:346:parse_blif$656' in module `map9v3'.
Optimizing away select inverter for $_MUX_ cell `$abc$546$auto$blifparse.cc:346:parse_blif$644' in module `map9v3'.
Optimizing away select inverter for $_MUX_ cell `$abc$546$auto$blifparse.cc:346:parse_blif$649' in module `map9v3'.
Optimizing away select inverter for $_MUX_ cell `$abc$546$auto$blifparse.cc:346:parse_blif$629' in module `map9v3'.
Optimizing away select inverter for $_MUX_ cell `$abc$546$auto$blifparse.cc:346:parse_blif$634' in module `map9v3'.
Optimizing away select inverter for $_MUX_ cell `$abc$546$auto$blifparse.cc:346:parse_blif$637' in module `map9v3'.
Optimizing away select inverter for $_MUX_ cell `$abc$546$auto$blifparse.cc:346:parse_blif$640' in module `map9v3'.
Optimizing away select inverter for $_MUX_ cell `$abc$546$auto$blifparse.cc:346:parse_blif$622' in module `map9v3'.
Optimizing away select inverter for $_MUX_ cell `$abc$546$auto$blifparse.cc:346:parse_blif$625' in module `map9v3'.
Optimizing away select inverter for $_MUX_ cell `$abc$546$auto$blifparse.cc:346:parse_blif$614' in module `map9v3'.
Optimizing away select inverter for $_MUX_ cell `$abc$546$auto$blifparse.cc:346:parse_blif$618' in module `map9v3'.
Optimizing away select inverter for $_MUX_ cell `$abc$546$auto$blifparse.cc:346:parse_blif$592' in module `map9v3'.
Optimizing away select inverter for $_MUX_ cell `$abc$546$auto$blifparse.cc:346:parse_blif$609' in module `map9v3'.
Optimizing away select inverter for $_MUX_ cell `$abc$546$auto$blifparse.cc:346:parse_blif$611' in module `map9v3'.

3.21.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\map9v3'.
Removed a total of 0 cells.

3.21.3. Executing OPT_RMDFF pass (remove dff with constant values).

3.21.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \map9v3..

3.21.5. Finished fast OPT passes.

3.22. Executing HIERARCHY pass (managing design hierarchy).

3.22.1. Analyzing design hierarchy..
Top module:  \map9v3

3.22.2. Analyzing design hierarchy..
Top module:  \map9v3
Removed 0 unused modules.

3.23. Printing statistics.

=== map9v3 ===

   Number of wires:                106
   Number of wire bits:            162
   Number of public wires:          10
   Number of public wire bits:      44
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                150
     $_AND_                         18
     $_AOI3_                         1
     $_DFF_PP0_                     31
     $_DFF_PP1_                      1
     $_MUX_                         51
     $_NAND_                         4
     $_NOR_                          8
     $_NOT_                         11
     $_OAI3_                         4
     $_OR_                           3
     $_XNOR_                         4
     $_XOR_                         14

3.24. Executing CHECK pass (checking for obvious problems).
checking module map9v3..
found and reported 0 problems.

4. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
  cell DFFNEGX1 (noninv, pins=3, area=384.00) is a direct match for cell type $_DFF_N_.
  cell DFFPOSX1 (noninv, pins=3, area=384.00) is a direct match for cell type $_DFF_P_.
  cell DFFSR (noninv, pins=5, area=704.00) is a direct match for cell type $_DFFSR_PNN_.
  create mapping for $_DFFSR_PPN_ from mapping for $_DFFSR_PNN_.
  create mapping for $_DFFSR_PNP_ from mapping for $_DFFSR_PNN_.
  create mapping for $_DFFSR_PPP_ from mapping for $_DFFSR_PNP_.
  create mapping for $_DFFSR_NNN_ from mapping for $_DFFSR_PNN_.
  create mapping for $_DFFSR_NPN_ from mapping for $_DFFSR_NNN_.
  create mapping for $_DFFSR_NNP_ from mapping for $_DFFSR_NNN_.
  create mapping for $_DFFSR_NPP_ from mapping for $_DFFSR_NNP_.
  create mapping for $_DFF_NN0_ from mapping for $_DFFSR_NNN_.
  create mapping for $_DFF_NN1_ from mapping for $_DFFSR_NNN_.
  create mapping for $_DFF_NP0_ from mapping for $_DFFSR_NPP_.
  create mapping for $_DFF_NP1_ from mapping for $_DFFSR_NPP_.
  create mapping for $_DFF_PN0_ from mapping for $_DFFSR_PNN_.
  create mapping for $_DFF_PN1_ from mapping for $_DFFSR_PNN_.
  create mapping for $_DFF_PP0_ from mapping for $_DFFSR_PPP_.
  create mapping for $_DFF_PP1_ from mapping for $_DFFSR_PPP_.
  final dff cell mappings:
    DFFNEGX1 _DFF_N_ (.CLK( C), .D( D), .Q( Q));
    DFFPOSX1 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
    DFFSR _DFF_NN0_ (.CLK(~C), .D( D), .Q( Q), .R( R), .S( 1));
    DFFSR _DFF_NN1_ (.CLK(~C), .D( D), .Q( Q), .R( 1), .S( R));
    DFFSR _DFF_NP0_ (.CLK(~C), .D( D), .Q( Q), .R(~R), .S( 1));
    DFFSR _DFF_NP1_ (.CLK(~C), .D( D), .Q( Q), .R( 1), .S(~R));
    DFFSR _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .R( R), .S( 1));
    DFFSR _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .R( 1), .S( R));
    DFFSR _DFF_PP0_ (.CLK( C), .D( D), .Q( Q), .R(~R), .S( 1));
    DFFSR _DFF_PP1_ (.CLK( C), .D( D), .Q( Q), .R( 1), .S(~R));
    DFFSR _DFFSR_NNN_ (.CLK(~C), .D( D), .Q( Q), .R( R), .S( S));
    DFFSR _DFFSR_NNP_ (.CLK(~C), .D( D), .Q( Q), .R(~R), .S( S));
    DFFSR _DFFSR_NPN_ (.CLK(~C), .D( D), .Q( Q), .R( R), .S(~S));
    DFFSR _DFFSR_NPP_ (.CLK(~C), .D( D), .Q( Q), .R(~R), .S(~S));
    DFFSR _DFFSR_PNN_ (.CLK( C), .D( D), .Q( Q), .R( R), .S( S));
    DFFSR _DFFSR_PNP_ (.CLK( C), .D( D), .Q( Q), .R(~R), .S( S));
    DFFSR _DFFSR_PPN_ (.CLK( C), .D( D), .Q( Q), .R( R), .S(~S));
    DFFSR _DFFSR_PPP_ (.CLK( C), .D( D), .Q( Q), .R(~R), .S(~S));
Mapping DFF cells in module `\map9v3':
  mapped 31 $_DFF_PP0_ cells to \DFFSR cells.
  mapped 1 $_DFF_PP1_ cells to \DFFSR cells.

5. Executing OPT pass (performing simple optimizations).

5.1. Executing OPT_EXPR pass (perform const folding).

5.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\map9v3'.
  Cell `$auto$dfflibmap.cc:511:dfflibmap$665' is identical to cell `$auto$dfflibmap.cc:511:dfflibmap$727'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$666 = $auto$rtlil.cc:1733:NotGate$728
    Removing $_NOT_ cell `$auto$dfflibmap.cc:511:dfflibmap$665' from module `\map9v3'.
  Cell `$auto$dfflibmap.cc:511:dfflibmap$667' is identical to cell `$auto$dfflibmap.cc:511:dfflibmap$727'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$668 = $auto$rtlil.cc:1733:NotGate$728
    Removing $_NOT_ cell `$auto$dfflibmap.cc:511:dfflibmap$667' from module `\map9v3'.
  Cell `$auto$dfflibmap.cc:511:dfflibmap$669' is identical to cell `$auto$dfflibmap.cc:511:dfflibmap$727'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$670 = $auto$rtlil.cc:1733:NotGate$728
    Removing $_NOT_ cell `$auto$dfflibmap.cc:511:dfflibmap$669' from module `\map9v3'.
  Cell `$auto$dfflibmap.cc:511:dfflibmap$671' is identical to cell `$auto$dfflibmap.cc:511:dfflibmap$727'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$672 = $auto$rtlil.cc:1733:NotGate$728
    Removing $_NOT_ cell `$auto$dfflibmap.cc:511:dfflibmap$671' from module `\map9v3'.
  Cell `$auto$dfflibmap.cc:511:dfflibmap$673' is identical to cell `$auto$dfflibmap.cc:511:dfflibmap$727'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$674 = $auto$rtlil.cc:1733:NotGate$728
    Removing $_NOT_ cell `$auto$dfflibmap.cc:511:dfflibmap$673' from module `\map9v3'.
  Cell `$auto$dfflibmap.cc:511:dfflibmap$675' is identical to cell `$auto$dfflibmap.cc:511:dfflibmap$727'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$676 = $auto$rtlil.cc:1733:NotGate$728
    Removing $_NOT_ cell `$auto$dfflibmap.cc:511:dfflibmap$675' from module `\map9v3'.
  Cell `$auto$dfflibmap.cc:511:dfflibmap$677' is identical to cell `$auto$dfflibmap.cc:511:dfflibmap$727'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$678 = $auto$rtlil.cc:1733:NotGate$728
    Removing $_NOT_ cell `$auto$dfflibmap.cc:511:dfflibmap$677' from module `\map9v3'.
  Cell `$auto$dfflibmap.cc:511:dfflibmap$679' is identical to cell `$auto$dfflibmap.cc:511:dfflibmap$727'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$680 = $auto$rtlil.cc:1733:NotGate$728
    Removing $_NOT_ cell `$auto$dfflibmap.cc:511:dfflibmap$679' from module `\map9v3'.
  Cell `$auto$dfflibmap.cc:511:dfflibmap$681' is identical to cell `$auto$dfflibmap.cc:511:dfflibmap$727'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$682 = $auto$rtlil.cc:1733:NotGate$728
    Removing $_NOT_ cell `$auto$dfflibmap.cc:511:dfflibmap$681' from module `\map9v3'.
  Cell `$auto$dfflibmap.cc:511:dfflibmap$683' is identical to cell `$auto$dfflibmap.cc:511:dfflibmap$727'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$684 = $auto$rtlil.cc:1733:NotGate$728
    Removing $_NOT_ cell `$auto$dfflibmap.cc:511:dfflibmap$683' from module `\map9v3'.
  Cell `$auto$dfflibmap.cc:511:dfflibmap$685' is identical to cell `$auto$dfflibmap.cc:511:dfflibmap$727'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$686 = $auto$rtlil.cc:1733:NotGate$728
    Removing $_NOT_ cell `$auto$dfflibmap.cc:511:dfflibmap$685' from module `\map9v3'.
  Cell `$auto$dfflibmap.cc:511:dfflibmap$687' is identical to cell `$auto$dfflibmap.cc:511:dfflibmap$727'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$688 = $auto$rtlil.cc:1733:NotGate$728
    Removing $_NOT_ cell `$auto$dfflibmap.cc:511:dfflibmap$687' from module `\map9v3'.
  Cell `$auto$dfflibmap.cc:511:dfflibmap$689' is identical to cell `$auto$dfflibmap.cc:511:dfflibmap$727'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$690 = $auto$rtlil.cc:1733:NotGate$728
    Removing $_NOT_ cell `$auto$dfflibmap.cc:511:dfflibmap$689' from module `\map9v3'.
  Cell `$auto$dfflibmap.cc:511:dfflibmap$691' is identical to cell `$auto$dfflibmap.cc:511:dfflibmap$727'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$692 = $auto$rtlil.cc:1733:NotGate$728
    Removing $_NOT_ cell `$auto$dfflibmap.cc:511:dfflibmap$691' from module `\map9v3'.
  Cell `$auto$dfflibmap.cc:511:dfflibmap$693' is identical to cell `$auto$dfflibmap.cc:511:dfflibmap$727'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$694 = $auto$rtlil.cc:1733:NotGate$728
    Removing $_NOT_ cell `$auto$dfflibmap.cc:511:dfflibmap$693' from module `\map9v3'.
  Cell `$auto$dfflibmap.cc:511:dfflibmap$695' is identical to cell `$auto$dfflibmap.cc:511:dfflibmap$727'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$696 = $auto$rtlil.cc:1733:NotGate$728
    Removing $_NOT_ cell `$auto$dfflibmap.cc:511:dfflibmap$695' from module `\map9v3'.
  Cell `$auto$dfflibmap.cc:511:dfflibmap$697' is identical to cell `$auto$dfflibmap.cc:511:dfflibmap$727'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$698 = $auto$rtlil.cc:1733:NotGate$728
    Removing $_NOT_ cell `$auto$dfflibmap.cc:511:dfflibmap$697' from module `\map9v3'.
  Cell `$auto$dfflibmap.cc:511:dfflibmap$699' is identical to cell `$auto$dfflibmap.cc:511:dfflibmap$727'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$700 = $auto$rtlil.cc:1733:NotGate$728
    Removing $_NOT_ cell `$auto$dfflibmap.cc:511:dfflibmap$699' from module `\map9v3'.
  Cell `$auto$dfflibmap.cc:511:dfflibmap$701' is identical to cell `$auto$dfflibmap.cc:511:dfflibmap$727'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$702 = $auto$rtlil.cc:1733:NotGate$728
    Removing $_NOT_ cell `$auto$dfflibmap.cc:511:dfflibmap$701' from module `\map9v3'.
  Cell `$auto$dfflibmap.cc:511:dfflibmap$703' is identical to cell `$auto$dfflibmap.cc:511:dfflibmap$727'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$704 = $auto$rtlil.cc:1733:NotGate$728
    Removing $_NOT_ cell `$auto$dfflibmap.cc:511:dfflibmap$703' from module `\map9v3'.
  Cell `$auto$dfflibmap.cc:511:dfflibmap$705' is identical to cell `$auto$dfflibmap.cc:511:dfflibmap$727'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$706 = $auto$rtlil.cc:1733:NotGate$728
    Removing $_NOT_ cell `$auto$dfflibmap.cc:511:dfflibmap$705' from module `\map9v3'.
  Cell `$auto$dfflibmap.cc:511:dfflibmap$707' is identical to cell `$auto$dfflibmap.cc:511:dfflibmap$727'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$708 = $auto$rtlil.cc:1733:NotGate$728
    Removing $_NOT_ cell `$auto$dfflibmap.cc:511:dfflibmap$707' from module `\map9v3'.
  Cell `$auto$dfflibmap.cc:511:dfflibmap$709' is identical to cell `$auto$dfflibmap.cc:511:dfflibmap$727'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$710 = $auto$rtlil.cc:1733:NotGate$728
    Removing $_NOT_ cell `$auto$dfflibmap.cc:511:dfflibmap$709' from module `\map9v3'.
  Cell `$auto$dfflibmap.cc:511:dfflibmap$711' is identical to cell `$auto$dfflibmap.cc:511:dfflibmap$727'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$712 = $auto$rtlil.cc:1733:NotGate$728
    Removing $_NOT_ cell `$auto$dfflibmap.cc:511:dfflibmap$711' from module `\map9v3'.
  Cell `$auto$dfflibmap.cc:511:dfflibmap$713' is identical to cell `$auto$dfflibmap.cc:511:dfflibmap$727'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$714 = $auto$rtlil.cc:1733:NotGate$728
    Removing $_NOT_ cell `$auto$dfflibmap.cc:511:dfflibmap$713' from module `\map9v3'.
  Cell `$auto$dfflibmap.cc:511:dfflibmap$715' is identical to cell `$auto$dfflibmap.cc:511:dfflibmap$727'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$716 = $auto$rtlil.cc:1733:NotGate$728
    Removing $_NOT_ cell `$auto$dfflibmap.cc:511:dfflibmap$715' from module `\map9v3'.
  Cell `$auto$dfflibmap.cc:511:dfflibmap$717' is identical to cell `$auto$dfflibmap.cc:511:dfflibmap$727'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$718 = $auto$rtlil.cc:1733:NotGate$728
    Removing $_NOT_ cell `$auto$dfflibmap.cc:511:dfflibmap$717' from module `\map9v3'.
  Cell `$auto$dfflibmap.cc:511:dfflibmap$719' is identical to cell `$auto$dfflibmap.cc:511:dfflibmap$727'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$720 = $auto$rtlil.cc:1733:NotGate$728
    Removing $_NOT_ cell `$auto$dfflibmap.cc:511:dfflibmap$719' from module `\map9v3'.
  Cell `$auto$dfflibmap.cc:511:dfflibmap$721' is identical to cell `$auto$dfflibmap.cc:511:dfflibmap$727'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$722 = $auto$rtlil.cc:1733:NotGate$728
    Removing $_NOT_ cell `$auto$dfflibmap.cc:511:dfflibmap$721' from module `\map9v3'.
  Cell `$auto$dfflibmap.cc:511:dfflibmap$723' is identical to cell `$auto$dfflibmap.cc:511:dfflibmap$727'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$724 = $auto$rtlil.cc:1733:NotGate$728
    Removing $_NOT_ cell `$auto$dfflibmap.cc:511:dfflibmap$723' from module `\map9v3'.
  Cell `$auto$dfflibmap.cc:511:dfflibmap$725' is identical to cell `$auto$dfflibmap.cc:511:dfflibmap$727'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$726 = $auto$rtlil.cc:1733:NotGate$728
    Removing $_NOT_ cell `$auto$dfflibmap.cc:511:dfflibmap$725' from module `\map9v3'.
Removed a total of 31 cells.

5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \map9v3..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \map9v3.
Performed a total of 0 changes.

5.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\map9v3'.
Removed a total of 0 cells.

5.6. Executing OPT_RMDFF pass (remove dff with constant values).

5.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \map9v3..

5.8. Executing OPT_EXPR pass (perform const folding).

5.9. Finished OPT passes. (There is nothing left to do.)

6. Executing ABC pass (technology mapping using ABC).

6.1. Extracting gate netlist of module `\map9v3' to `/input.blif'..
Extracted 119 gates and 162 wires to a netlist network with 43 inputs and 31 outputs.

6.1.1. Executing ABC.
Running ABC command: /yosys-abc -s -f /abc.script 2>&1
ABC: ABC command line: "source /abc.script".
ABC: 
ABC: + read_blif /input.blif 
ABC: + read_lib -w /opt/asic/share/qflow/tech/osu035/osu035_stdcells.lib 
ABC: Parsing finished successfully.  Parsing time =     0.00 sec
ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFFNEGX1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFFPOSX1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFFSR".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "LATCH".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "PADINOUT".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "TBUFX1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "TBUFX2".
ABC: Scl_LibertyReadGenlib() skipped cell "PADFC" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "PADNC" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "PADVDD" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "PADGND" without logic function.
ABC: Library "osu035_stdcells" from "/opt/asic/share/qflow/tech/osu035/osu035_stdcells.lib" has 28 cells (11 skipped: 4 seq; 3 tri-state; 4 no func).  Time =     0.01 sec
ABC: Memory =    0.38 MB. Time =     0.01 sec
ABC: Warning: Detected 2 multi-output gates (for example, "FAX1").
ABC: + strash 
ABC: + scorr 
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
ABC: + ifraig 
ABC: + retime 
ABC: + strash 
ABC: + dch -f 
ABC: + map -M 1 
ABC: + write_blif /output.blif 

6.1.2. Re-integrating ABC results.
ABC RESULTS:            AND2X2 cells:        4
ABC RESULTS:           AOI21X1 cells:       14
ABC RESULTS:           AOI22X1 cells:        3
ABC RESULTS:             INVX1 cells:       38
ABC RESULTS:            MUX2X1 cells:        7
ABC RESULTS:           NAND2X1 cells:       11
ABC RESULTS:           NAND3X1 cells:        8
ABC RESULTS:            NOR2X1 cells:       12
ABC RESULTS:            NOR3X1 cells:        2
ABC RESULTS:           OAI21X1 cells:       27
ABC RESULTS:             OR2X2 cells:        1
ABC RESULTS:           XNOR2X1 cells:        4
ABC RESULTS:            XOR2X1 cells:        1
ABC RESULTS:        internal signals:       88
ABC RESULTS:           input signals:       43
ABC RESULTS:          output signals:       31
Removing temp directory.

7. Executing FLATTEN pass (flatten design).
No more expansions possible.
Removed 0 unused cells and 162 unused wires.

8. Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells).
Don't map input port map9v3.N: Missing option -inpad.
Don't map input port map9v3.clock: Missing option -inpad.
Mapping port map9v3.counter using BUFX2.
Mapping port map9v3.done using BUFX2.
Mapping port map9v3.dp using BUFX2.
Don't map input port map9v3.reset: Missing option -inpad.
Mapping port map9v3.sr using BUFX2.
Don't map input port map9v3.start: Missing option -inpad.

9. Executing OPT pass (performing simple optimizations).

9.1. Executing OPT_EXPR pass (perform const folding).

9.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\map9v3'.
Removed a total of 0 cells.

9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \map9v3..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \map9v3.
Performed a total of 0 changes.

9.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\map9v3'.
Removed a total of 0 cells.

9.6. Executing OPT_RMDFF pass (remove dff with constant values).

9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \map9v3..

9.8. Executing OPT_EXPR pass (perform const folding).

9.9. Finished OPT passes. (There is nothing left to do.)

10. Executing BLIF backend.

End of script. Logfile hash: 1f5a63de0f, CPU: user 0.31s system 0.01s
Yosys 0.7+     153 (git sha1 a6ca2827, clang 8.0.0 -fPIC -Os)
Time spent: 17% 1x share (0 sec), 15% 18x opt_expr (0 sec), ...
Cleaning up output syntax
Yosys syntax postprocessing
Cleaning Up blif file syntax
Running blifFanout (iterative)
gates resized: 18
gates resized: 9
gates resized: 0
Generating RTL verilog and SPICE netlist file in directory
	 /Users/simon/src/asic/examples/9v3/synthesis
Files:
   Verilog: /Users/simon/src/asic/examples/9v3/synthesis/map9v3.rtl.v
   Verilog: /Users/simon/src/asic/examples/9v3/synthesis/map9v3.rtlnopwr.v
   Spice:   /Users/simon/src/asic/examples/9v3/synthesis/map9v3.spc
Running blif2Verilog.
Running blif2BSpice.
project path: /Users/simon/src/asic/examples/9v3
source name : map9v3
root name   : map9v3
Running blif2cel.tcl
No map9v3.cel2 file found for project. . . continuing without pin placement hints
Running GrayWolf placement
[/opt/asic/share/qflow/bin/graywolf  map9v3]
Qrouter detail maze router version 1.3.65.T
Reading LEF data from file /opt/asic/share/qflow/tech/osu035/osu035_stdcells.lef.
LEF Read, Line 106: Don't know how to parse layer "via1"
LEF Read, Line 107: No layer defined for RECT.
LEF Read, Line 115: Don't know how to parse layer "via2"
LEF Read, Line 116: No layer defined for RECT.
LEF Read, Line 124: Don't know how to parse layer "via3"
LEF Read, Line 125: No layer defined for RECT.
LEF Read, Line 131: Unknown keyword "GENERATE" in LEF file; ignoring.
LEF Read, Line 135: Unknown keyword "OVERHANG" in LEF file; ignoring.
LEF Read, Line 136: Unknown keyword "METALOVERHANG" in LEF file; ignoring.
LEF Read, Line 140: Unknown keyword "OVERHANG" in LEF file; ignoring.
LEF Read, Line 141: Unknown keyword "METALOVERHANG" in LEF file; ignoring.
LEF Read, Line 142: Don't know how to parse layer "via1"
LEF Read, Line 143: No layer defined for RECT.
LEF Read, Line 147: Unknown keyword "GENERATE" in LEF file; ignoring.
LEF Read, Line 151: Unknown keyword "OVERHANG" in LEF file; ignoring.
LEF Read, Line 152: Unknown keyword "METALOVERHANG" in LEF file; ignoring.
LEF Read, Line 156: Unknown keyword "OVERHANG" in LEF file; ignoring.
LEF Read, Line 157: Unknown keyword "METALOVERHANG" in LEF file; ignoring.
LEF Read, Line 158: Don't know how to parse layer "via2"
LEF Read, Line 159: No layer defined for RECT.
LEF Read, Line 163: Unknown keyword "GENERATE" in LEF file; ignoring.
LEF Read, Line 167: Unknown keyword "OVERHANG" in LEF file; ignoring.
LEF Read, Line 168: Unknown keyword "METALOVERHANG" in LEF file; ignoring.
LEF Read, Line 172: Unknown keyword "OVERHANG" in LEF file; ignoring.
LEF Read, Line 173: Unknown keyword "METALOVERHANG" in LEF file; ignoring.
LEF Read, Line 174: Don't know how to parse layer "via3"
LEF Read, Line 175: No layer defined for RECT.
LEF Read, Line 179: Unknown keyword "GENERATE" in LEF file; ignoring.
LEF Read, Line 186: Unknown keyword "GENERATE" in LEF file; ignoring.
LEF Read, Line 193: Unknown keyword "GENERATE" in LEF file; ignoring.
LEF Read, Line 200: Unknown keyword "GENERATE" in LEF file; ignoring.
LEF file:  Defines site corner (ignored)
LEF file:  Defines site IO (ignored)
LEF file:  Defines site core (ignored)
LEF Read, Line 235: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 244: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 277: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 297: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 345: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 365: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 420: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 443: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 499: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 522: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 556: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 575: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 611: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 632: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 674: Don't know how to parse layer "via1"
LEF Read, Line 700: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 713: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 766: Don't know how to parse layer "via1"
LEF Read, Line 809: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 835: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 908: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 921: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 970: Don't know how to parse layer "via1"
LEF Read, Line 1054: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 1068: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 1115: Don't know how to parse layer "via1"
LEF Read, Line 1140: Don't know how to parse layer "via1"
LEF Read, Line 1188: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 1200: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 1235: Don't know how to parse layer "via1"
LEF Read, Line 1258: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 1275: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 1301: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 1318: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 1344: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 1362: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 1389: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 1412: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 1447: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 1466: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 1507: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 1531: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 1565: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 1587: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 1630: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 1651: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 1706: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 1728: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 1771: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 1793: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 1838: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 1859: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 1902: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 1923: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 1968: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 1989: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 2044: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 2067: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 2109: Don't know how to parse layer "via1"
LEF Read, Line 2151: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 2174: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 2210: Don't know how to parse layer "via1"
LEF Read, Line 2233: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 2256: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 2295: Don't know how to parse layer "via1"
LEF Read, Line 2340: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 2351: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read, Line 2374: Don't know how to parse layer "via1"
LEF Read, Line 2437: Unknown keyword "SHAPE" in LEF file; ignoring.
LEF Read:  Further errors will not be reported.
LEF read: Processed 3179 lines.
LEF Read: encountered 110 errors total.
Running getfillcell.tcl
Using cell FILL for fill
Generating RTL verilog and SPICE netlist file in directory
   /Users/simon/src/asic/examples/9v3/synthesis
Files:
   Verilog: /Users/simon/src/asic/examples/9v3/synthesis/map9v3.rtl.v
   Verilog: /Users/simon/src/asic/examples/9v3/synthesis/map9v3.rtlnopwr.v
   Spice:   /Users/simon/src/asic/examples/9v3/synthesis/map9v3.spc
Running blif2Verilog.
Running blif2BSpice.
Running addspacers.tcl
Running qrouter 1.3.65.T
Nets remaining: 200
Nets remaining: 100
Nets remaining: 90
Nets remaining: 80
Nets remaining: 70
Nets remaining: 60
Nets remaining: 50
Nets remaining: 40
Nets remaining: 30
Nets remaining: 20
Nets remaining: 10
Nets remaining: 9
Nets remaining: 8
Nets remaining: 7
Nets remaining: 6
Nets remaining: 5
Nets remaining: 4
Nets remaining: 3
Nets remaining: 2
Progress: Stage 1 total routes completed: 482
Nets remaining: 2
Nets remaining: 1
Nets remaining: 1
Progress: Stage 2 total routes completed: 490
No failed routes!
Progress: Stage 2 total routes completed: 490
No failed routes!
Final: No failed routes!