FPGA to ASIC

        - one lonesome software engineer's trek into the darkness


Tutorial revisit

My immediate reaction was that I had screwed up the Mac port somewhere. Getting the code to where clang liked it to be involved a fair amount of (to be honest) drudgery, adding prototypes, fixing warning, attempting to make it 64-bit clean etc. I was suspicious that somewhere along the line, there was either an inherent bug that "just worked" when no prototype was used, or there was some sort of automatic type-promotion going on that was causing me grief.

In fact it turned out that there were two distinct bugs - one was just in the tutorial, where there were a couple of missing options to the 'ext2spice' command (remember the commands in orange, that's them…). Without the thresholds for C and R being set to infinity, the parasitic capacitances would be extracted for Spice, and those don't exist in the design, so we ignore them for purposes of design verification.

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The other bug was one introduced when Xfab support was added to qrouter, and one of the connections wasn't actually making it to its terminus.You can just about see the gap in the image to the right. Tim found it, and fixed it, and the fix is in the latest git source available on his website.

With both of those bugs fixed, the Mac version synthesized, placed, and routed the circuit just as well as the Linux version, as far as I can tell. There is one more test to do though, and that's a "switch" level simulator called IRSIM. This is another tool from the opencircuits.org website, and it treats the digital circuit as a set of idealised transistors (hence "switch-level" simulation).
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The tutorial provides a tcl file which will generate the IRSIM UI, and launching the program will start the simulation, clicking on the bottom-left button will present a screen like that shown to the left.

In the case of this circuit, "success" is measures by the 'done' signal going high after a couple of hundred clock cycles. and the result being '206' at that point. As you can see, the simulation passes muster, which couldn't be said for the version without the qrouter patch from Tim (which is as you would expect, if the simulation was accurate and the circuit was not correct).

So now we can run through the tutorial and get the expected results, which validates the toolset. Now it's on to creating the my own verilog design and generating a synthesis of the cell array for that design.


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