FPGA to ASIC

        - one lonesome software engineer's trek into the darkness


Designing and making your own silicon chips...

In the words of Jeremy Clarkson ... "How hard can it be?"

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Verilog source code ASIC layout diagram

About me

I work as a software engineer in a combined hardware/software department, I use FPGAs connected to computers to prototype and develop hardware for new computer systems. My job is to write everything from interrupt-driven bit-bashing of I2C on minuscule embedded chips, RTOS systems specific to the platform we're on, custom RTL peripherals on enormous FPGAs, through to PCIe kernel drivers on the attached computers, user-space libraries that talk to the kernel and ultimately tools that sit on top of that. There's never a dull moment. The last rig that sat on my desk had *three* of the largest FPGAs on the planet inter-connected to do the job.

Even with all this going on, it's still fun to explore new horizons, so I thought it'd be a good plan (the next logical step, if you will) to see if I could develop my own ASIC. With MPW wafer "shuttle" services available to make the cost almost possible to speak of without choking, and with open-source software available to glean from, all that was lacking was a degree-level knowledge of chip-design and all the experience surrounding you as you learn in college. So, onwards and upwards then…

This site is an attempt to document the process for posterity and hopefully make it easier on the next intrepid explorer descending from all that is goodness and light in the familiar realm of software engineering, to the Under-Dark, where signs saying "Here be Dragons!" make sure to capitalise the 'D', and are well worth watching out for…

So, leave your sanity behind on the surface, and come spelunk with me on the journey. It's probably not going to be dull…